Senior LevelWeb Security & Cyber Defense
What are Cache-Based Side-Channel Attacks (Flush+Reload, Prime+Probe) and how are they mitigated?
❓ Interview Prompt: Explain Cache Side-Channel attacks, Flush+Reload, Prime+Probe, measuring CPU L1/L3 cache latency, and constant-time algorithm defenses.
Cache-Based Side-Channel Attacks infer secret cryptographic keys by measuring the time it takes the CPU to read data from L1/L3 caches vs main RAM:
Flush+Reload Attack Mechanics:
1
Attacker flushes a shared memory page from CPU cache ('clflush').
2
Victim process executes a cryptographic operation (e.g. RSA modular exponentiation).
3
Attacker reloads memory page and measures access time ('rdtsc'). Fast access means the victim accessed that memory line!
•
Defense: Write cryptographic code using Constant-Time Execution path algorithms with zero secret-dependent memory lookups.
Code Implementation Example
c
// C Constant-Time Conditional Select (No branching, immune to cache timing attacks!)
uint32_t ct_select(uint32_t a, uint32_t b, uint32_t condition) {
uint32_t mask = -condition; // 0xFFFFFFFF if 1, 0x00000000 if 0
return (a & mask) | (b & ~mask);
}💡Writing constant-time C code without conditional branching to mitigate side-channel timing attacks.
🎯 Interview Key Takeaway
Mitigate cache side-channel attacks by writing constant-time cryptographic algorithms with no secret-dependent branches.
#Side-Channel#Flush+Reload#Cache Security#Senior
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