Senior LevelSystem Design & Architecture
What is False Sharing in multi-core L1/L2 CPU caches and how do you align memory buffers?
❓ Interview Prompt: Explain False Sharing in multi-core CPUs, 64-byte L1/L2 cache lines, MESI cache coherence protocol, and memory padding.
False Sharing is a severe performance degradation in multi-core CPU architectures:
How False Sharing Occurs:
1
Modern CPUs fetch memory in 64-byte Cache Lines into L1/L2 caches.
2
If Thread A on Core 1 updates Variable $X$, and Thread B on Core 2 updates Variable $Y$, and both variables reside on the same 64-byte cache line:
3
The CPU MESI cache coherence protocol forces both cores to continuously invalidate and re-fetch the cache line from L3/RAM, causing severe CPU cache thrashing!
•
Fix: Pad variables with 64 bytes of empty memory to force them onto distinct cache lines.
Code Implementation Example
typescript
// Preventing False Sharing via 64-byte Cache Line Memory Padding
class PaddedAtomicCounter {
public count = 0;
// 56 bytes of dummy padding to ensure 64-byte cache line isolation!
private _p1 = 0; private _p2 = 0; private _p3 = 0; private _p4 = 0;
private _p5 = 0; private _p6 = 0; private _p7 = 0;
}💡Padding memory variables to 64-byte boundaries to prevent CPU false sharing.
🎯 Interview Key Takeaway
Pad multi-threaded memory variables to 64-byte boundaries to eliminate false sharing cache invalidation penalties.
#System Design#False Sharing#CPU Cache#Performance#Senior
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